The present invention relates to an AAL2 packet exchange device for executing interchanging of CPS packets (AAL2 packets according to ATM adaptation layer 2) extracted from input ATM cells and thereby remultiplexing the CPS packets in output ATM cells.
As an ATM (Asynchronous Transfer Mode) adaptation layer for ATM signal transfer, there has been standardized the AAL2 (ATM Adaptation Layer type 2 (ITU-T I.363.2)). According to the AAL2, the payload (48-byte information field) of an ATM cell is used for carrying a CPS-PDU (Common Part Sublayer-Protocol Data Unit) (48 bytes). The 48-byte CPS-PDU is composed of a CPS-PDU header (1 byte) and a CPS-PDU payload (47 bytes), and CPS (Common Part Sublayer) packets are filled (multiplexed) in the CPS-PDU payload. The CPS packet is a variable length packet whose maximum length is 48 bytes (or 64 bytes (option)), which is composed of a CPS packet header (3 bytes) and a CPS packet payload (45 bytes or less). In the CPS packet header, a CID (Channel IDentifier) (1 byte) which is used for designating the logical channel of each CPS packet is included. At an ATM switch for executing ATM cell transfer according to the AAL2, CPS packets are extracted from two or more CPS-PDUs (i.e. from two or more ATM cells), and the extracted CPS packets are re-multiplexed in one or more CPS-PDUs, and the CPS-PDU is filled in a new ATM cell and transmitted (see Japanese Patent Application Laid-Open No.HEI 10-294743 and International Publication No. WO96/26589, for example).
FIG. 1 is a schematic block diagram showing an example of a conventional AAL2 packet exchange device. FIG. 2 is a table showing information which is stored in an ATM cell header search table 5 which is shown in FIG. 1. FIG. 3 is a schematic diagram showing variable length packet interchange operation which is executed by a variable length packet interchange device 1 (i.e. the AAL2 packet exchange device) which is shown in FIG. 1.
Referring to FIG. 1, a variable length packet interchange device 1 (i.e. the AAL2 packet exchange device) is placed in front of an ATM switch 6. The variable length packet interchange device 1 includes a variable length packet extraction section 2 and a variable length packet re-multiplexing section 3. The variable length packet extraction section 2 extracts variable length packets (CPS packets) from inputted ATM cells. The variable length packet re-multiplexing section 3 extracts channel identifiers (CIDs) from headers of the CPS packets. A CPU 4 searches the ATM cell header search table 5 of FIG. 2 using the CID (packet address) of each CPS packet, and thereby obtains a VPI/VCI and ATM cell header information concerning each of the CPS packets. Thereby, CPS packets corresponding to the same VPI/VCI (in the ATM cell header search table 5) is gathered in each buffer of the variable length packet re-multiplexing section 3, and the CPS packets corresponding to the same VPI/VCI is multiplexed by the variable length packet re-multiplexing section 3 in an ATM cell having the VPI/VCI. By such operation, the CPS packets A, B, C, D and E shown in FIG. 1 are re-multiplexed in the ATM cells 7a, 7b and 7c shown in FIG. 1 respectively to be outputted to the output lines.
However, the conventional AAL2 packet exchange device involves the following drawbacks or problems.
When CPS packets (variable length packets) are extracted from a plurality of ATM cells and the extracted CPS packets are re-multiplexed in ATM cells according to the VPI/VCI (obtained from the ATM cell header search table 5), the CIDs in the re-multiplexed CPS packets are not altered, therefore, CID collision can occur in an ATM cell to be outputted. For example, referring to FIG. 3, two ATM cells are supplied to the variable length packet interchange device 1. The first ATM cell contains 4 CPS packets whose CIDs are xe2x80x9cAxe2x80x9d, xe2x80x9cBxe2x80x9d, xe2x80x9cCxe2x80x9d and xe2x80x9cDxe2x80x9d, and the second ATM cell contains 4 CPS packets whose CIDs are xe2x80x9cExe2x80x9d, xe2x80x9cFxe2x80x9d, xe2x80x9cCxe2x80x9d and xe2x80x9cGxe2x80x9d. The 8 CPS packets are extracted from the two ATM cells, and re-multiplexed in two ATM cells (for example) according to the VPI/VCIs searched from the ATM cell header search table 5 using the CIDs of each CPS packet. As a result, CID collision occurs in the second output ATM cell (i.e. in the second ATM cell to be outputted), that is, two CPS packets having the same CIDs xe2x80x9cCxe2x80x9d are multiplexed in one ATM cell. Referring to the two input ATM cells on the upper side of FIG. 3, it can be judged that the two CPS packets having the same CIDs xe2x80x9cCxe2x80x9d have supplied from different sources if the VPI/VCI of the first input ATM cell differs from that of the second input ATM cell. However, when the second output ATM cell containing the two CPS packets having CIDs xe2x80x9cCxe2x80x9d is outputted and supplied to the next ATM switch etc, it can not be judged that the two CPS packets having CIDs xe2x80x9cCxe2x80x9d have supplied from different sources, since the two CPS packets have the same CIDs xe2x80x9cCxe2x80x9d and are contained in an ATM cell having a VPI/VCI.
In order to avoid this problem, the two CPS packets having the same CIDs xe2x80x9cCxe2x80x9d have to be multiplexed in different ATM cells having different VPI/VCIs. As a result, usage efficiency of each VP/VC has to be decreased. Further, the number of ATM cells generated and outputted by the AAL2 packet exchange device is necessitated to be increased in order to avoid the CID collision, and thus the load on the next ATM switches is necessitated to be increased.
It is therefore the primary object of the present invention to provide an AAL2 packet exchange device by which multiplexing efficiency on each ATM connection can be increased, and thereby increase in the number of ATM cells and increase in the load on ATM switches can be avoided.
In accordance with a first aspect of the present invention, there is provided an AAL2 packet exchange device which is placed in front of an ATM switch for executing CPS packet re-multiplexing into ATM cells. The AAL2 packet exchange device extracts CPS-PDUs (Common Part Sublayer- Protocol Data Units) from ATM cells which are supplied from input ATM lines, extracts CPS packets from the CPS-PDUs, alters CIDs (Channel IDentifiers) of the CPS packets if necessary so that CID collision will not occur between CPS packets supplied from different sources to be outputted to the same output ATM connection, multiplexes the CPS packets to be outputted to the same output ATM connection in ATM cells of the same output ATM connection, and thereby realizes re-multiplexing of CPS packets extracted from ATM cells supplied from different sources into the same ATM connection without the CID collision.
In accordance with a second aspect of the present invention, in the first aspect, the AAL2 packet exchange device comprises a selector means, a path setting table means, a first memory means, a CPS-PDU processing means, a CPS packet processing means, a second memory means, a CPS-PDU generation means, an ATM cell generation means and a multiplexing means. The selector means selects ATM cells containing CPS-PDUs and ATM cells not containing CPS-PDUs from ATM cells supplied from the input ATM lines, outputs the ATM cells not containing CPS-PDUs untouched, and extracts the CPS-PDUs from the ATM cells containing CPS-PDUs. The path setting table means stores a table indicating each correspondence between a first internal address for discriminating between input ATM connections, an input CID, a second internal address for discriminating between output ATM connections, and an output CID. The first memory means stores the CPS-PDUs extracted by the selector means and the first internal addresses concerning the CPS-PDUs. The CPS-PDU processing means extracts CPS packets from the CPS-PDU which has been stored in the first memory means, stores the front part of a CPS packet if the CPS packet has been split across two CPS-PDUs, and regenerates the CPS packet when the rear part of the CPS packet is supplied, by adding the rear part to the front part of the CPS packet which has been stored therein. The CPS packet processing means obtains the second internal address and the output CID concerning each CPS packet extracted or regenerated by the CPS-PDU processing means by referring to the path setting table means using the first internal address and the CID (input CID) concerning the CPS packet, updates the CID (input CID) of each CPS packet into the output CID, updates HEC (Header Error Control) information of the CPS packet, and outputs the CPS packet and the second internal address concerning the CPS packet. The second memory means stores the CPS packets and the second internal addresses concerning the CPS packets outputted by the CPS packet processing means. The CPS-PDU generation means reads out the CPS packets and the second internal addresses concerning the CPS packets from the second memory means, multiplexes CPS packets corresponding to the same second internal address into a CPS-PDU, and outputs the CPS-PDU. The ATM cell generation means fills the CPS-PDU supplied from the CPS-PDU generation means in an ATM cell and outputs the ATM cell to one of its output lines according to information obtained from the path setting table means, and meanwhile outputs an idle ATM cell to each output line that has no ATM cell to be outputted thereto. The multiplexing means multiplexes the ATM cells not containing CPS-PDUs outputted by the selector means and the ATM cells outputted by the ATM cell generation means, and outputs the multiplexed ATM cells to its output lines.
In accordance with a third aspect of the present invention, in the second aspect, the AAL2 packet exchange device further comprises a CPS-PDU output request means. The CPS-PDU output request means sends a CPS-PDU output request signal and a second internal address to the CPS-PDU generation means if the CPS-PDU generation means has not outputted a CPS-PDU corresponding to the second internal address for a predetermined period, and thereby makes the CPS-PDU generation means output a CPS-PDU corresponding to the second internal address to the ATM cell generation means immediately.
In accordance with a fourth aspect of the present invention, in the second aspect, the first memory means includes a CPS-PDU FIFO (First In First Out) memory and a first internal address FIFO memory. The CPS-PDU FIFO memory stores the CPS-PDUs supplied from the selector means according to FIFO operation, and the first internal address FIFO memory stores the first internal addresses concerning the CPS-PDUs according to FIFO operation.
In accordance with a fifth aspect of the present invention, in the second aspect, the second memory means includes a CPS packet FIFO (First In First Out) memory and a second internal address FIFO memory. The CPS packet FIFO memory stores the CPS packets outputted by the CPS packet processing means, and the second internal address FIFO memory stores the second internal addresses concerning the CPS packets according to FIFO operation.
In accordance with a sixth aspect of the present invention, in the second aspect, the CPS-PDU processing means includes a CPS packet front part memory. The CPS packet front part memory stores the front part of the CPS packet which has been split across two CPS-PDUs, with respect to each first internal address.
In accordance with a seventh aspect of the present invention, in the second aspect, the CPS-PDU generation means includes a CPS-PDU front part memory. The CPS-PDU front part memory stores the CPS-PDU in the middle of generation, with respect to each second internal address.
In accordance with an eighth aspect of the present invention, in the second aspect, the selector means includes internal buffers, buffer control sections, a selector section, a CPS-PDU transmission section and an ATM cell transmission section. Each of the internal buffers is provided corresponding to each of the input ATM lines for storing the ATM cell supplied from the input ATM line. The buffer control sections control reading/writing of the ATM cells to the internal buffers. The selector section executes ATM cell transmission request to each buffer control section, receives the ATM cell from the buffer control section, extracts the VPI (Virtual Path Identifier) and the VCI (Virtual Channel Identifier) from the ATM cell, obtains the first internal address concerning the ATM cell from the path setting table means using the VPI, the VCI and the input line number concerning the ATM cell, sends the ATM cell and the first internal address concerning the ATM cell to the CPS-PDU transmission section if the ATM cell contains a CPS-PDU, and sends the ATM cell and the input line number concerning the ATM cell to the ATM cell transmission section if the ATM cell does not contain a CPS-PDU. The CPS-PDU transmission section receives the ATM cell containing the CPS-PDU and the first internal address from the selector section, extracts the CPS-PDU from the ATM cell, and outputs the CPS-PDU and the first internal address to the first memory means. The ATM cell transmission section receives the ATM cell not containing a CPS-PDU and the input line number concerning the ATM cell from the selector section, and outputs the ATM cell to the multiplexing means via one of its output lines corresponding to the input line number.
In accordance with a ninth aspect of the present invention, in the second aspect, the CPS-PDU processing means includes a CPS packet front part memory, a CPS-PDU reception section, a CPS-PDU payload buffer and a CPS packet extraction/regeneration section. The CPS packet front part memory stores the front part of a CPS packet which has been split across two CPS-PDUs, with respect to each first internal address. The CPS-PDU reception section reads out the CPS-PDU and the first internal address concerning the CPS-PDU from the first memory means, extracts a CPS-PDU header and CPS-PDU payload information from the CPS-PDU, outputs the CPS-PDU header and the first internal address to the CPS packet extraction/regeneration section, and writes the CPS-PDU payload information in the CPS-PDU payload buffer. The CPS-PDU payload buffer stores the CPS-PDU payload information. The CPS packet extraction/regeneration section executes a CPS packet extraction/regeneration process with regard to the CPS-PDU using the CPS-PDU payload information stored in the CPS-PDU payload buffer, the CPS-PDU header and the first internal address supplied from the CPS-PDU reception section, and the front part of a CPS packet which has been stored in the CPS packet front part memory, and outputs the extracted/regenerated CPS packets, the first internal address concerning the CPS packets, and the CIDs of the CPS packets to the CPS packet processing means.
In accordance with a tenth aspect of the present invention, in the second aspect, the CPS-PDU generation means includes a CPS packet reception section, a CPS-PDU front part memory and a CPS-PDU transmission section. The CPS packet reception section reads out the CPS packet and the second internal address concerning the CPS packet from the second memory means and outputs them when a CPS packet request signal is supplied thereto. The CPS-PDU front part memory stores a CPS-PDU in the middle of generation, with respect to each second internal address. The CPS-PDU transmission section sends the CPS packet request signal to the CPS packet reception section when there is data in the second memory means, receives the CPS packet and the second internal address concerning the CPS packet from the CPS packet reception section, reads out the CPS-PDU in the middle of generation with respect to the second internal address from the CPS-PDU front part memory, adds the CPS packet to the CPS-PDU in the middle of generation with respect to the second internal address, sends a completed CPS-PDU and the second internal address concerning the CPS-PDU when a CPS-PDU is completed, and writes a CPS-PDU in the middle of generation in the CPS-PDU front part memory.